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UPSC ESE E&T Electronics Engineering Flashcards
51 question-and-answer cards covering Electronics Engineering as it is examined in UPSC ESE E&T. 24 of them are printed below, taken from across the deck — no signup, no paywall on the preview.
24 sample cards from the Electronics Engineering deck
Sampled from the end of the deck, so these are different cards from the ones shown on the syllabus page.
Write the truth-table behavior of a 2-input NAND gate and state why it is universal.
Output is 0 only when both inputs are 1; otherwise 1 (Y = (A·B)'). It is 'universal' because any logic function (NOT, AND, OR) can be built using only NAND gates.
Give the Boolean output expressions for XOR and XNOR gates.
XOR: Y = A⊕B = A'B + AB' (1 when inputs differ). XNOR: Y = (A⊕B)' = AB + A'B' (1 when inputs are equal).
State both forms of De Morgan's theorems.
(A·B)' = A' + B' and (A + B)' = A'·B'. The complement of a product is the sum of complements, and vice versa.
What is the difference between a half-adder and a full-adder?
Half-adder adds two bits: Sum = A⊕B, Carry = AB. Full-adder adds three bits (A, B, Cin): Sum = A⊕B⊕Cin, Cout = AB + Cin(A⊕B).
Compare a combinational circuit with a sequential circuit.
Combinational: output depends only on present inputs, no memory (e.g., adders, mux). Sequential: output depends on present inputs and past state, uses memory/clock (e.g., flip-flops, counters).
Describe the operation of an SR latch and its forbidden input condition.
S=1,R=0 → Set (Q=1); S=0,R=1 → Reset (Q=0); S=0,R=0 → hold previous state. S=1,R=1 is forbidden/invalid (indeterminate output).
Give the characteristic (excitation) behavior of a JK flip-flop for each input combination.
J=0,K=0 → no change; J=0,K=1 → reset (Q=0); J=1,K=0 → set (Q=1); J=1,K=1 → toggle (Q = Q'). Characteristic eq: Q(n+1) = JQ' + K'Q.
What is the function of a D flip-flop and a T flip-flop?
D flip-flop: Q(n+1) = D — output follows input at the clock edge (data/delay storage). T flip-flop: Q(n+1) = T⊕Q — toggles output when T=1, holds when T=0.
What problem does a master-slave flip-flop solve and how?
It eliminates the race-around condition (multiple toggles within one clock pulse) in level-triggered JK flip-flops by cascading two latches that respond on opposite clock levels, making it effectively edge-triggered.
Differentiate asynchronous (ripple) counters from synchronous counters.
Asynchronous: flip-flops triggered by the previous stage's output, causing cumulative propagation delay (slow). Synchronous: all flip-flops share a common clock, so they switch simultaneously (faster, no ripple delay).
How many flip-flops are required for a MOD-N counter, and what is the count range of a 4-bit counter?
Number of flip-flops = smallest n such that 2^n ≥ N. A 4-bit counter has 2^4 = 16 states, counting 0 to 15 (MOD-16).
What is a ring counter and a Johnson (twisted-ring) counter, and how many states does each have for n flip-flops?
Ring counter: a single 1 circulates; n distinct states. Johnson counter: complemented output fed back; 2n distinct states.
List the four basic data movement modes of a shift register.
SISO (Serial-In Serial-Out), SIPO (Serial-In Parallel-Out), PISO (Parallel-In Serial-Out), and PIPO (Parallel-In Parallel-Out).
What is a universal shift register?
A register capable of all operations: serial-in/out, parallel-in/out, and bidirectional (left and right) shifting, selected via mode-control inputs (e.g., the 74194).
Differentiate a microprocessor from a microcontroller.
Microprocessor: CPU only; RAM, ROM, I/O, timers are external (general-purpose computing). Microcontroller: CPU plus RAM, ROM, I/O ports, timers on a single chip (embedded/dedicated control applications).
Contrast Von Neumann and Harvard architectures.
Von Neumann: single shared memory and bus for both instructions and data (e.g., 8085). Harvard: separate memories and buses for program and data, allowing simultaneous fetch (e.g., 8051), giving higher throughput.
State the address bus width, data bus width, and number of addressable memory locations of the Intel 8085.
16-bit address bus → 2^16 = 64 KB addressable memory; 8-bit data bus (8-bit microprocessor).
What is small-signal analysis and what assumption underlies it?
It analyzes amplifier behavior for small AC variations about the DC operating (Q) point, assuming the device behaves linearly over that small range so nonlinear characteristics can be replaced by linear equivalent (h-parameter / hybrid-π) models.
In the hybrid-π model of a BJT, give the expressions for transconductance gm and input resistance rπ.
gm = I_C/V_T (≈ I_C/26 mV at room temp); rπ = β/gm = βV_T/I_C.
What is large-signal analysis and how does it differ from small-signal analysis?
Large-signal analysis handles big input swings where the device operates over its full nonlinear characteristic (used for power amplifiers, switching, Q-point/load-line design). Unlike small-signal, linear approximation around Q-point is not valid.
Name the four basic feedback amplifier topologies and the quantity each stabilizes.
Voltage-series (stabilizes voltage gain, ↑Rin, ↓Rout), current-series (transconductance), voltage-shunt (transresistance, ↓Rin, ↓Rout), and current-shunt (current gain).
State the effect of negative feedback on gain, bandwidth, and distortion.
Closed-loop gain A_f = A/(1+Aβ) is reduced by factor (1+Aβ); bandwidth is increased by the same factor (gain-bandwidth product constant); distortion and noise are reduced by (1+Aβ); stability improves.
Compare the maximum theoretical efficiency of Class A, Class B, and Class AB power amplifiers.
Class A: 25% (capacitive/transformerless) up to 50% (transformer-coupled), conducts 360°. Class B: ~78.5%, conducts 180° (push-pull). Class AB: between Class A and B (~60–78%), conducts >180° to reduce crossover distortion.
What causes crossover distortion in a Class B push-pull amplifier and how is it eliminated?
It occurs near zero crossing because neither transistor conducts until its base-emitter threshold (~0.7 V) is reached. It is eliminated by slightly forward-biasing the transistors (Class AB operation) using diodes or a V_BE multiplier.
What this deck covers
The Electronics Engineering deck follows the UPSC ESE E&T Electronics Engineering syllabus — 3 chapters and 15 topics — so questions land on material that is genuinely examinable rather than trivia around it. That works out to roughly 17.0 cards per chapter.
Answers are written to be recallable, not just readable — averaging about 165 characters, which is long enough to carry the reasoning and short enough to say out loud.
A deck like this earns its keep on the second and third pass. Read the syllabus first so you know the shape of the subject, then use the cards to find the specific facts that have not stuck.
Electronics Engineering flashcards FAQ
How many Electronics Engineering flashcards are in this UPSC ESE E&T deck?
51 cards. This page previews 24 of them, sampled evenly across the deck so you can judge the difficulty before installing anything.
Are these UPSC ESE E&T flashcards free?
Yes. The preview here is free to read with no signup, and the full 51-card deck is free inside the Examius app.
What do the Electronics Engineering cards cover?
They follow the UPSC ESE E&T Electronics Engineering syllabus — 3 chapters and 15 topics — so the questions track what is actually examinable.
How should I use these flashcards?
Read the syllabus first so you know the shape of the subject, then drill the deck. Examius schedules each card with spaced repetition, so cards you keep missing come back sooner and ones you know drift further apart.