GATE E&C Engineering Digital Circuits Syllabus

Digital Circuits syllabus — full chapter and topic list

Expand any chapter to see its topics and sub-topics. This is the whole examinable outline for Digital Circuits in GATE E&C Engineering, not a summary of it.

1. 1

   Number representations

   2 topics

   • Binary
   • Integer and Floating-Point Numbers
2. 2

   Combinatorial circuits

   7 topics

   • Boolean algebra
   • Minimization of functions using Boolean identities and Karnaugh map
   • Logic gates and their static CMOS implementations
   • Arithmetic circuits
   • Code converters
   • Multiplexers
   • Decoders
3. 3

   Sequential circuits

   7 topics

   • Latches and Flip-Flops
   • Counters
   • Shift-Registers
   • Finite State Machines
   • Propagation Delay
   • Setup and Hold Time
   • Critical Path Delay
4. 4

   Data converters

   3 topics

   • Sample and Hold Circuits
   • ADCs
   • DACs
5. 5

   Semiconductor memories

   3 topics

   • ROM
   • SRAM
   • DRAM
6. 6

   Computer organization

   4 topics

   • Machine instructions and addressing modes
   • ALU
   • Data-path and Control unit
   • Instruction Pipelining

Digital Circuits flashcards for GATE E&C Engineering

24 of 52 cards from the Digital Circuits deck — real questions with worked answers.

1. In an $n$-bit binary number, what is the range of unsigned integers that can be represented?

   $0$ to $2^{n}-1$, giving $2^{n}$ distinct values.

2. How do you convert the binary fraction $0.101_2$ to decimal?

   Use place values $2^{-1}, 2^{-2}, 2^{-3}$: $0.101_2 = \frac{1}{2}+\frac{0}{4}+\frac{1}{8} = 0.625_{10}$.

3. What is the 2's complement of an $n$-bit number, and what range does it represent?

   2's complement of $N$ is $2^{n}-N$ (invert all bits and add 1). It represents signed values from $-2^{n-1}$ to $+2^{n-1}-1$.

4. In 2's complement, how is the value of an $n$-bit pattern $b_{n-1}b_{n-2}\dots b_0$ computed?

   $V = -b_{n-1}\,2^{n-1} + \sum_{i=0}^{n-2} b_i\,2^{i}$, i.e. the MSB carries negative weight.

5. State the IEEE-754 single-precision (32-bit) field layout and bias.

   1 sign bit, 8 exponent bits, 23 mantissa bits. Exponent bias is $127$; value $=(-1)^{s}\times 1.M \times 2^{E-127}$ for normalized numbers.

6. What is the exponent bias for IEEE-754 double precision (64-bit)?

   $1023$. Layout is 1 sign bit, 11 exponent bits, 52 mantissa bits.

7. How does normalized IEEE-754 representation gain an extra bit of mantissa precision?

   By the implicit (hidden) leading 1: normalized numbers are stored as $1.M$, so the leading $1$ is not stored, giving 24 effective bits in single precision.

8. State De Morgan's two theorems in Boolean algebra.

   $\overline{A+B}=\bar A\cdot\bar B$ and $\overline{A\cdot B}=\bar A+\bar B$.

9. What are the Boolean identities for $A+\bar A B$ and $A(\bar A+B)$?

   $A+\bar A B = A+B$ and $A(\bar A+B)=AB$ (absorption/redundancy laws).

10. State the distributive and absorption laws of Boolean algebra.

    Distributive: $A(B+C)=AB+AC$ and $A+BC=(A+B)(A+C)$. Absorption: $A+AB=A$ and $A(A+B)=A$.

11. What is the consensus theorem in Boolean algebra?

    $AB+\bar A C + BC = AB+\bar A C$; the consensus term $BC$ is redundant and can be removed.

12. What is the difference between a minterm and a maxterm?

    A minterm is a product (AND) term that is $1$ for exactly one input combination; a maxterm is a sum (OR) term that is $0$ for exactly one combination. SOP uses minterms, POS uses maxterms.

13. How many cells does a Karnaugh map for $n$ variables have, and how are adjacent cells arranged?

    $2^{n}$ cells, arranged in Gray-code order so that adjacent cells (including wrap-around) differ in exactly one variable.

14. In a K-map, what does grouping $2^{k}$ adjacent 1-cells eliminate?

    It eliminates $k$ variables; a group of size $2^{k}$ leaves $n-k$ variables in the product term. Larger groups give simpler terms.

15. What are 'don't care' conditions in K-map minimization and how are they used?

    Don't cares (X) are input combinations that never occur or whose output is irrelevant; they may be treated as $0$ or $1$ to form larger groups and simplify the expression.

16. Define a prime implicant and an essential prime implicant.

    A prime implicant is a group that cannot be combined into a larger group. An essential prime implicant is one that covers at least one minterm covered by no other prime implicant.

17. Why are NAND and NOR called universal gates?

    Any Boolean function can be implemented using only NAND gates or only NOR gates, since each can realize AND, OR, and NOT.

18. Write the Boolean expressions for 2-input XOR and XNOR.

    $A\oplus B = \bar A B + A\bar B$ and $\overline{A\oplus B}=AB+\bar A\bar B$.

19. In a static CMOS gate, what determines the structure of the pull-up network (PUN) and pull-down network (PDN)?

    The PUN is made of PMOS transistors and conducts for input combinations giving output $1$; the PDN is made of NMOS transistors and conducts for output $0$. PUN and PDN are dual networks (series in one = parallel in the other).

20. How many transistors are needed for a static CMOS 2-input NAND gate?

    4 transistors: 2 PMOS in parallel (PUN) and 2 NMOS in series (PDN).

21. In static CMOS, how is a series connection of NMOS in the PDN reflected in the PUN?

    Series NMOS in the PDN corresponds to parallel PMOS in the PUN (the two networks are duals).

22. Why does an ideal static CMOS gate draw essentially no static (DC) power?

    Because in any steady logic state either the PUN or the PDN is off, so there is no direct path from $V_{DD}$ to ground; power is dissipated mainly during switching.

23. Write the sum and carry equations of a half adder.

    $S = A\oplus B$ and $C_{out}=A\cdot B$.

24. Write the sum and carry-out equations of a full adder.

    $S = A\oplus B\oplus C_{in}$ and $C_{out}=AB + C_{in}(A\oplus B)$.

See more Digital Circuits flashcards →

Planning Digital Circuits for GATE E&C Engineering

Digital Circuits (GATE E&C Engineering) FAQ