🇮🇳 GATE E&C Engineering · subject
GATE E&C Engineering Analog Circuits Syllabus
Every chapter and topic of Analog Circuits examined in GATE E&C Engineering — 4 chapters, 16 topics, plus 51 flashcards written against it.
Analog Circuits syllabus — full chapter and topic list
Expand any chapter to see its topics and sub-topics. This is the whole examinable outline for Analog Circuits in GATE E&C Engineering, not a summary of it.
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Diode circuits
3 topics- Clipping
- Clamping
- Rectifiers
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BJT and MOSFET amplifiers
4 topics- Biasing
- AC coupling
- Small signal analysis
- Frequency response
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Current mirrors and differential amplifiers
2 topics- Current mirrors
- Differential amplifiers
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Op-amp circuits
7 topics- Amplifiers
- Summers
- Differentiators
- Integrators
- Active filters
- Schmitt triggers
- Oscillators
Analog Circuits flashcards for GATE E&C Engineering
22 of 51 cards from the Analog Circuits deck — real questions with worked answers.
In a positive series clipper using an ideal diode in series with the load, which part of the input waveform appears at the output?
A positive series clipper removes (clips) the positive half of the input. With an ideal series diode oriented to conduct on negative inputs, only the negative half-cycle (below $0\,\text{V}$) reaches the output; the positive portion is clipped to $0\,\text{V}$.
For a biased shunt clipper with a diode in parallel with the load and a reference battery $V_R$ (diode conducts when $v_i > V_R$), what is the clipped output level?
When the diode conducts, the output is held at the reference level: $$v_o = V_R + V_\gamma$$ where $V_\gamma$ is the diode cut-in voltage (about $0.7\,\text{V}$ for silicon). Below this, $v_o = v_i$.
What is the fundamental difference between a clipper and a clamper circuit?
A clipper removes a portion of the input waveform (limits amplitude) and does not shift the DC level. A clamper shifts the entire waveform up or down to a new DC reference without changing its shape or peak-to-peak amplitude; it uses a capacitor to add a DC offset.
In a negative clamper, to what value is the positive peak of the output clamped (ideal diode)?
A negative clamper shifts the waveform down so its positive peak sits at $0\,\text{V}$. The capacitor charges to the peak input voltage $V_m$, giving output swinging from $0$ down to $-2V_m$.
State the design condition (time-constant requirement) for a clamper circuit to work properly.
The RC time constant must be much larger than the period of the input: $$\tau = RC \gg T$$ Typically $RC \geq 10T$ (or $5T$ per half-period) so the capacitor holds its charge and the DC shift is maintained.
For a half-wave rectifier with sinusoidal input of peak $V_m$, give the DC (average) output voltage and the ripple factor.
DC output: $$V_{dc} = \frac{V_m}{\pi}$$ RMS output: $V_{rms} = \frac{V_m}{2}$. Ripple factor: $$r = \sqrt{\left(\frac{V_{rms}}{V_{dc}}\right)^2 - 1} = 1.21$$
For a full-wave (or bridge) rectifier with sinusoidal input peak $V_m$, give $V_{dc}$, $V_{rms}$, ripple factor, and rectification efficiency.
$$V_{dc} = \frac{2V_m}{\pi}, \quad V_{rms} = \frac{V_m}{\sqrt{2}}$$ Ripple factor $r = 0.482$; maximum efficiency $\eta = 81.2\%$.
Compare the Peak Inverse Voltage (PIV) of a center-tapped full-wave rectifier versus a bridge rectifier (each delivering peak $V_m$).
Center-tapped FW rectifier: $\text{PIV} = 2V_m$. Bridge rectifier: $\text{PIV} = V_m$. The bridge needs cheaper, lower-rated diodes but uses four diodes versus two.
What is the ripple factor of a full-wave rectifier with a shunt capacitor filter (capacitor $C$, load $R_L$, supply frequency $f$)?
$$r = \frac{1}{4\sqrt{3}\, f R_L C}$$ Ripple decreases as $C$ and $R_L$ increase; the ripple frequency for full-wave is $2f$.
State the four conditions a BJT amplifier must satisfy to operate in the active region for faithful amplification.
For active region: emitter-base junction forward biased, collector-base junction reverse biased. The Q-point must lie within the active region (not in saturation or cutoff) and the signal swing must keep $V_{CE}$ and $I_C$ within active limits.
Define the stability factor $S$ for BJT bias and give its expression for the voltage-divider (self-bias) configuration.
$$S = \frac{\partial I_C}{\partial I_{CO}}\Big|_{V_{BE},\beta}$$ For voltage-divider bias: $$S = \frac{(1+\beta)(1 + R_B/R_E)}{1 + \beta + R_B/R_E}$$ where $R_B = R_1 \parallel R_2$. Smaller $S$ (closer to 1) means better thermal stability.
Why is the voltage-divider (potential-divider) bias the most widely used BJT biasing scheme?
It makes the Q-point essentially independent of $\beta$. With $R_E$ providing negative feedback and $V_B$ set by the divider, $I_C \approx (V_B - V_{BE})/R_E$, giving good thermal stability and a low stability factor $S$.
What is the purpose of the bypass capacitor across the emitter resistor $R_E$ in a CE amplifier?
$R_E$ provides DC bias stabilization through negative feedback, but it also reduces AC gain. The bypass capacitor shorts $R_E$ at signal frequencies, restoring full AC gain $A_v \approx -g_m R_C$ while keeping DC stability intact.
What roles do coupling (AC-coupling) capacitors serve between amplifier stages?
Coupling capacitors block DC so each stage's bias (Q-point) is undisturbed, while passing the AC signal between stages. They also set the lower cutoff frequency, behaving as a high-pass element.
How does a coupling capacitor influence the lower cutoff frequency of an amplifier?
A coupling capacitor $C$ with the resistance $R$ it sees forms a high-pass filter with cutoff $$f_L = \frac{1}{2\pi R C}$$ Below $f_L$ the capacitor's reactance attenuates the signal at $-20\,\text{dB/decade}$.
In the hybrid-$\pi$ small-signal model of a BJT, give the transconductance $g_m$ and base input resistance $r_\pi$.
$$g_m = \frac{I_C}{V_T}, \qquad r_\pi = \frac{\beta}{g_m} = \frac{\beta V_T}{I_C}$$ where $V_T \approx 26\,\text{mV}$ at room temperature.
What is the small-signal voltage gain of a common-emitter amplifier (with bypassed $R_E$), and what is its phase relationship?
$$A_v = -g_m (R_C \parallel R_L)$$ The negative sign indicates a $180^\circ$ phase inversion between input and output.
Give the small-signal voltage gain and key characteristics of a common-collector (emitter follower) amplifier.
$$A_v = \frac{g_m R_E}{1 + g_m R_E} \approx 1$$ It has high input impedance, low output impedance, no phase inversion, and is used as a buffer / impedance matcher; current and power gain are high though voltage gain $\approx 1$.
Summarize the comparison of CE, CB, and CC BJT amplifier configurations in terms of gains, impedances, and phase.
CE: high voltage and current gain, medium $Z_{in}$/$Z_{out}$, $180^\circ$ phase shift. CB: high voltage gain, current gain $<1$, low $Z_{in}$, high $Z_{out}$, no phase shift. CC: voltage gain $\approx 1$, high current gain, high $Z_{in}$, low $Z_{out}$, no phase shift (buffer).
For a MOSFET in saturation, write the drain current equation and the small-signal transconductance $g_m$.
$$I_D = \frac{1}{2}\mu_n C_{ox}\frac{W}{L}(V_{GS}-V_{th})^2$$ $$g_m = \mu_n C_{ox}\frac{W}{L}(V_{GS}-V_{th}) = \sqrt{2\mu_n C_{ox}\frac{W}{L} I_D} = \frac{2I_D}{V_{GS}-V_{th}}$$
What limits the high-frequency response of a CE amplifier, and which effect dominates?
The internal junction capacitances $C_\pi$ and $C_\mu$ limit high-frequency gain. The Miller effect multiplies $C_\mu$ by $(1+|A_v|)$, giving an effective input capacitance $C_{in} = C_\pi + C_\mu(1+|A_v|)$, which dominates and sets the upper cutoff frequency.
State the Miller effect: how an impedance $Z$ bridging input and output of an inverting amplifier of gain $-A$ appears at the input.
The bridging impedance appears at the input as $$Z_{in} = \frac{Z}{1+A}$$ For a capacitor $C$, the effective input capacitance becomes $C_{in} = C(1+A)$, greatly reducing bandwidth.
Planning Analog Circuits for GATE E&C Engineering
Analog Circuits is about 9% of the GATE E&C Engineering syllabus by topic count — 16 of 170 topics, spread over 4 chapters. At roughly 45 minutes per topic plus 12 minutes per sub-topic, a first pass runs to about 10 hours.
The heaviest chapters are Op-amp circuits (7 topics), BJT and MOSFET amplifiers (4 topics), Diode circuits (3 topics) . Front-load those while your energy is high; the short chapters are better revision filler later.
Work top-down: read the chapter, then tick topics off individually rather than marking the whole chapter done. Sub-topics are where silent gaps hide.
Analog Circuits (GATE E&C Engineering) FAQ
What is in the GATE E&C Engineering Analog Circuits syllabus?
Analog Circuits is split into 4 chapters — Diode circuits, BJT and MOSFET amplifiers, Current mirrors and differential amplifiers and Op-amp circuits, containing 16 topics and 0 sub-topics in total.
How many chapters are there in Analog Circuits for GATE E&C Engineering?
4 chapters. Analog Circuits accounts for about 9% of the topics in the whole GATE E&C Engineering syllabus (16 of 170).
How long should I spend on Analog Circuits for GATE E&C Engineering?
Budget around 10 hours for a first pass through Analog Circuits — about 45 minutes per topic plus 12 minutes per sub-topic across its 16 topics. Add revision cycles on top.
Are there flashcards for GATE E&C Engineering Analog Circuits?
Yes — a 51-card Analog Circuits deck. Sample cards are printed on this page, and the full deck is free in the Examius app with spaced repetition scheduling.