UGC NET Computer Science Computer System Architecture Flashcards

24 sample cards from the Computer System Architecture deck

Sampled from the end of the deck, so these are different cards from the ones shown on the syllabus page.

1. What is address sequencing in a microprogrammed control unit?

   Address sequencing is the process of determining the address of the next microinstruction in control memory, using methods like incrementing, branching (conditional/unconditional), mapping the opcode, and subroutine return.

2. What is a vectored interrupt and how does it differ from a non-vectored interrupt?

   In a vectored interrupt, the interrupting device supplies the address (vector) of its service routine. In a non-vectored interrupt, control branches to a fixed predetermined address.

3. Differentiate between machine language, assembly language, and an assembler.

   Machine language is binary code directly executed by the CPU; assembly language uses mnemonic symbols for instructions; an assembler is a program that translates assembly language into machine language.

4. What is a subroutine and how do the CALL and RETURN operations work using a stack?

   A subroutine is a reusable block of code. CALL pushes the return address onto the stack and branches to the subroutine; RETURN pops the return address from the stack to resume the caller.

5. What is the difference between LIFO and FIFO organization, and which does a stack use?

   LIFO (Last-In-First-Out) removes the most recently added item; FIFO (First-In-First-Out) removes the oldest. A stack uses LIFO.

6. What are zero-, one-, two-, and three-address instruction formats?

   Three-address: ADD R1,R2,R3; two-address: ADD R1,R2 (R1←R1+R2); one-address: uses an implied accumulator (ADD M); zero-address: stack-based, operands implied on top of stack (ADD).

7. List and define common addressing modes.

   Immediate (operand in instruction), register, register-indirect, direct (address in instruction), indirect, indexed (base+index), relative (PC+offset), and autoincrement/autodecrement.

8. Compare RISC and CISC architectures.

   RISC: few simple fixed-length instructions, many registers, load/store architecture, hardwired control, single-cycle execution. CISC: many complex variable-length instructions, fewer registers, memory operands allowed, microprogrammed control.

9. What is Flynn's classification of computer architectures?

   SISD (single instruction, single data), SIMD (single instruction, multiple data), MISD (multiple instruction, single data), and MIMD (multiple instruction, multiple data).

10. What is pipelining and what is the ideal speedup of a k-stage pipeline?

    Pipelining overlaps execution of multiple instructions by dividing the datapath into stages. The ideal speedup approaches k (the number of stages) for a large number of tasks.

11. What are the three types of pipeline hazards?

    Structural hazards (resource conflicts), data hazards (dependency on results of prior instructions), and control hazards (branch/jump instructions changing the instruction flow).

12. What is the difference between an arithmetic pipeline and an instruction pipeline?

    An arithmetic pipeline divides an arithmetic operation (e.g., floating-point add) into sub-operations to overlap them; an instruction pipeline overlaps the fetch-decode-execute phases of consecutive instructions.

13. What is the difference between vector processing and array processing?

    Vector processing uses pipelined functional units to process one-dimensional arrays (vectors) of data. Array processing (SIMD) uses multiple processing elements operating in parallel under a single control unit.

14. What is the difference between synchronous and asynchronous data transfer?

    Synchronous transfer uses a common clock to coordinate sender and receiver; asynchronous transfer has no common clock and relies on control signals like strobe or handshaking.

15. What is handshaking in asynchronous data transfer?

    Handshaking uses two control signals so both units agree on timing: the source asserts data-valid and the destination responds with an acknowledge, ensuring reliable transfer without a shared clock.

16. What are the four modes of data transfer between CPU/memory and I/O?

    Programmed I/O, interrupt-initiated I/O, Direct Memory Access (DMA), and I/O processor (channel) transfer.

17. What is a daisy-chain priority interrupt scheme?

    A daisy chain connects devices in series by priority; the interrupt acknowledge passes through devices in order, and the highest-priority requesting device closest to the CPU intercepts it first and places its vector.

18. What is DMA and why is it used?

    Direct Memory Access lets an I/O device transfer data directly to/from memory without CPU intervention for each word. The DMA controller takes over the bus (cycle stealing or burst mode), freeing the CPU and speeding bulk transfers.

19. What is the difference between memory-mapped I/O and isolated (I/O-mapped) I/O?

    Memory-mapped I/O assigns I/O devices addresses in the memory space using the same instructions as memory. Isolated I/O uses a separate address space and dedicated I/O instructions (IN/OUT).

20. Order main memory, cache, auxiliary memory, and registers by speed and cost in the memory hierarchy.

    From fastest/most-expensive to slowest/cheapest: registers > cache > main memory (RAM) > auxiliary memory (disk/tape). Speed and cost-per-bit decrease while capacity increases down the hierarchy.

21. What is associative (content-addressable) memory and how is it accessed?

    Associative memory is accessed by the content of the data rather than by an address; all words are compared in parallel against a search argument, making it fast for searching (used in TLBs/cache tags).

22. What are the three cache mapping techniques?

    Direct mapping (each block maps to one fixed cache line), associative mapping (a block can go in any line), and set-associative mapping (a block maps to a set of lines, e.g., 2-way or 4-way).

23. What is virtual memory and what is the role of a page table?

    Virtual memory lets programs use an address space larger than physical memory by storing pages on disk and loading them on demand. The page table maps virtual page numbers to physical frame numbers.

24. What is cache coherence and name two protocols that maintain it.

    Cache coherence ensures all caches in a multiprocessor see a consistent value for a shared memory location. Protocols include snooping protocols (e.g., MESI write-invalidate) and directory-based protocols.

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