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GATE Physics Electronics Flashcards
66 question-and-answer cards covering Electronics as it is examined in GATE Physics. 24 of them are printed below, taken from across the deck — no signup, no paywall on the preview.
24 sample cards from the Electronics deck
Sampled from the end of the deck, so these are different cards from the ones shown on the syllabus page.
State the two ideal op-amp 'golden rules' and key ideal parameters.
Rules (with negative feedback): (1) no current flows into the inputs; (2) the two input voltages are equal (virtual short). Ideal parameters: infinite open-loop gain, infinite input impedance, zero output impedance, infinite bandwidth and CMRR.
Give the closed-loop gain of inverting and non-inverting op-amp amplifiers.
Inverting: $$A_v = -\frac{R_f}{R_1}$$ Non-inverting: $$A_v = 1 + \frac{R_f}{R_1}$$
Write the output of an ideal op-amp integrator and differentiator.
Integrator: $$v_o(t) = -\frac{1}{RC}\int v_{in}\,dt$$ Differentiator: $$v_o(t) = -RC\,\frac{dv_{in}}{dt}$$
Define CMRR and slew rate for an op-amp.
CMRR (common-mode rejection ratio): $\text{CMRR} = \left|\dfrac{A_d}{A_{cm}}\right|$, often in dB; ratio of differential to common-mode gain. Slew rate: $SR = \left.\dfrac{dv_o}{dt}\right|_{max}$, the maximum output voltage rate of change (V/µs).
Classify active filters by their frequency response (four basic types).
Low-pass (passes below $f_c$), High-pass (passes above $f_c$), Band-pass (passes a band), Band-stop/notch (rejects a band). 'Active' means they use op-amps plus R and C (no inductors).
For a first-order RC active filter, give the cutoff frequency and roll-off rate.
$$f_c = \frac{1}{2\pi RC}$$ Roll-off is $20$ dB/decade ($6$ dB/octave) per pole; an $n$-th order filter rolls off at $20n$ dB/decade.
Define the quality factor $Q$ of a band-pass filter.
$$Q = \frac{f_0}{\text{BW}} = \frac{f_0}{f_H - f_L}$$ where $f_0$ is the center frequency and BW is the $-3$ dB bandwidth. Higher $Q$ means a narrower, more selective passband.
State De Morgan's theorems of Boolean algebra.
$$\overline{A+B} = \bar{A}\cdot\bar{B}, \qquad \overline{A\cdot B} = \bar{A} + \bar{B}$$ The complement of a sum is the product of complements, and vice versa.
Why are NAND and NOR gates called universal gates?
Because any Boolean function (and hence any logic gate: NOT, AND, OR) can be implemented using only NAND gates, or only NOR gates.
Write the truth-table outputs of a half-adder.
For inputs $A,B$: Sum $= A \oplus B$ and Carry $= A\cdot B$. A full adder adds a carry-in: $S = A\oplus B\oplus C_{in}$, $C_{out} = AB + C_{in}(A\oplus B)$.
What is the key difference between combinational and sequential logic circuits?
Combinational: output depends only on present inputs (no memory), e.g. adders, multiplexers, decoders. Sequential: output depends on present inputs and past state (has memory via flip-flops), and usually requires a clock, e.g. counters, registers.
Give the characteristic (next-state) equations of SR, D, JK, and T flip-flops.
SR: $Q_{n+1} = S + \bar{R}Q_n$ (with $SR=0$). D: $Q_{n+1} = D$. JK: $Q_{n+1} = J\bar{Q}_n + \bar{K}Q_n$. T: $Q_{n+1} = T\oplus Q_n$ (toggles when $T=1$).
What is the forbidden/invalid input condition of an SR latch, and how does the JK flip-flop fix it?
SR latch: $S=R=1$ is forbidden (indeterminate output). The JK flip-flop replaces this with a defined TOGGLE action: when $J=K=1$, $Q_{n+1}=\bar{Q}_n$.
What is the master-slave flip-flop and the problem it solves?
Two latches in series clocked on opposite phases. It eliminates the 'race-around' condition (multiple toggles in one clock pulse) of a level-triggered JK flip-flop by making the output change only once per clock edge.
Describe the operation of a 555 timer in astable mode and its frequency.
In astable mode it free-runs as an oscillator (no stable state), producing a continuous square wave. Frequency: $$f = \frac{1.44}{(R_A + 2R_B)C}$$ with duty cycle $D = \dfrac{R_A+R_B}{R_A+2R_B}$.
Describe the 555 timer in monostable mode and its output pulse width.
It has one stable state and produces a single timed output pulse when triggered. Pulse width: $$T = 1.1\,RC$$
Distinguish asynchronous (ripple) counters from synchronous counters.
Asynchronous/ripple: each flip-flop is clocked by the previous stage's output, so transitions ripple through — simple but slow with cumulative delay. Synchronous: all flip-flops share a common clock, so they change simultaneously — faster, no ripple, but more logic.
How many flip-flops are needed for a modulo-$N$ counter, and what is the maximum count of an $n$-flip-flop binary counter?
Number of flip-flops $= \lceil \log_2 N \rceil$. An $n$-flip-flop binary counter counts $0$ to $2^{n}-1$, i.e. $2^{n}$ states (modulo-$2^{n}$).
List the four basic data-movement modes of a shift register.
SISO (serial-in serial-out), SIPO (serial-in parallel-out), PISO (parallel-in serial-out), and PIPO (parallel-in parallel-out). They store and shift binary data, used for serial/parallel conversion.
Distinguish a ring counter from a Johnson (twisted-ring) counter.
Ring counter: feeds $Q$ of the last flip-flop to the first; an $n$-bit ring counter has $n$ states. Johnson counter: feeds $\bar{Q}$ of the last back to the first; an $n$-bit Johnson counter has $2n$ states.
Write the analog output of a binary-weighted / R-2R N-bit DAC.
$$V_{out} = V_{ref}\sum_{i=0}^{N-1} \frac{b_i}{2^{N-i}} = V_{ref}\,\frac{D}{2^{N}}$$ where $b_i$ are the bits and $D$ is the decimal equivalent of the input code.
Define the resolution (step size) of an N-bit DAC/ADC over a full-scale range $V_{FS}$.
$$\text{Resolution} = \frac{V_{FS}}{2^{N}-1}\approx\frac{V_{FS}}{2^{N}}$$ This is the smallest voltage change (1 LSB) the converter can represent, with $2^{N}$ total levels.
Compare flash, successive-approximation, and dual-slope ADCs on speed and use.
Flash: fastest (one clock), uses $2^{N}-1$ comparators, costly — for high-speed apps. Successive-approximation (SAR): medium speed ($N$ clocks), good speed/cost balance — most common. Dual-slope (integrating): slowest but very accurate and noise-immune — for digital meters.
What is quantization error in an ADC and its maximum value?
The error from mapping a continuous analog value to the nearest discrete level. With rounding, the maximum quantization error is $\pm\frac{1}{2}$ LSB, i.e. $\pm\dfrac{V_{FS}}{2^{N+1}}$.
What this deck covers
The Electronics deck follows the GATE Physics Electronics syllabus — 4 chapters and 18 topics — so questions land on material that is genuinely examinable rather than trivia around it. That works out to roughly 16.5 cards per chapter.
Answers are written to be recallable, not just readable — averaging about 179 characters, which is long enough to carry the reasoning and short enough to say out loud.
A deck like this earns its keep on the second and third pass. Read the syllabus first so you know the shape of the subject, then use the cards to find the specific facts that have not stuck.
Electronics flashcards FAQ
How many Electronics flashcards are in this GATE Physics deck?
66 cards. This page previews 24 of them, sampled evenly across the deck so you can judge the difficulty before installing anything.
Are these GATE Physics flashcards free?
Yes. The preview here is free to read with no signup, and the full 66-card deck is free inside the Examius app.
What do the Electronics cards cover?
They follow the GATE Physics Electronics syllabus — 4 chapters and 18 topics — so the questions track what is actually examinable.
How should I use these flashcards?
Read the syllabus first so you know the shape of the subject, then drill the deck. Examius schedules each card with spaced repetition, so cards you keep missing come back sooner and ones you know drift further apart.