GATE CS & IT Engineering Computer Organization and Architecture Syllabus

Computer Organization and Architecture syllabus — full chapter and topic list

Expand any chapter to see its topics and sub-topics. This is the whole examinable outline for Computer Organization and Architecture in GATE CS & IT Engineering, not a summary of it.

1. 1

   Machine instructions and addressing modes

   1 topic

   • ALU, data‐path and control unit
2. 2

   Instruction pipelining, pipeline hazards

   1 topic

   • Pipeline hazards
3. 3

   Memory hierarchy: cache, main memory and secondary storage

   3 topics

   • Cache
   • Main Memory
   • Secondary Storage
4. 4

   I/O interface (interrupt and DMA mode)

   2 topics

   • Interrupt Mode
   • DMA Mode

Computer Organization and Architecture flashcards for GATE CS & IT Engineering

22 of 50 cards from the Computer Organization and Architecture deck — real questions with worked answers.

1. What is the function of the ALU (Arithmetic Logic Unit) in a CPU?

   The ALU is the combinational digital circuit that performs arithmetic operations (addition, subtraction, etc.) and logic operations (AND, OR, NOT, XOR, comparisons, shifts) on operands, producing a result and status flags.

2. In a processor datapath, what are the three main components and their roles?

   Register file (stores operands/results), ALU (performs computation), and interconnecting buses/multiplexers (route data). The datapath carries out data processing under the control unit's direction.

3. What is the difference between the datapath and the control unit?

   The datapath is the collection of functional units (ALU, registers, buses) that perform operations on data, while the control unit generates control signals that tell the datapath what operation to perform and when.

4. What are the two main ways of designing a control unit?

   Hardwired control (control signals generated by fixed combinational/sequential logic — fast, hard to modify) and microprogrammed control (control signals stored as microinstructions in control memory — flexible, slower).

5. Compare hardwired and microprogrammed control units.

   Hardwired: fast, uses fixed logic, difficult to modify, suited to RISC. Microprogrammed: slower, uses control memory of microinstructions, easy to modify/extend, suited to CISC.

6. What status flags does an ALU typically produce?

   Zero (Z), Carry (C), Sign/Negative (N), and Overflow (V) flags, which reflect properties of the most recent ALU result.

7. What are the typical stages of a classic 5-stage instruction pipeline (MIPS)?

   IF (Instruction Fetch), ID (Instruction Decode/register read), EX (Execute/ALU), MEM (Memory access), WB (Write Back).

8. For an ideal k-stage pipeline executing n instructions, what is the speedup over a non-pipelined processor?

   $$S = \frac{n \cdot k}{k + (n-1)}$$ As $n \to \infty$, the speedup approaches $k$ (the number of stages).

9. What is the maximum ideal speedup of a k-stage pipeline, and what is the ideal throughput?

   Maximum ideal speedup is $k$ (the number of stages). Ideal throughput is one instruction completed per clock cycle, i.e. $CPI = 1$.

10. What are the three classes of pipeline hazards?

    Structural hazards (resource conflicts), Data hazards (dependencies between instructions), and Control hazards (branch/jump uncertainty).

11. What is a structural hazard in a pipeline?

    A structural hazard occurs when two instructions need the same hardware resource (e.g., a single memory port or one ALU) in the same clock cycle, causing a conflict that stalls the pipeline.

12. What is a data hazard, and name its three types.

    A data hazard arises when an instruction depends on the result of a previous instruction still in the pipeline. Types: RAW (Read After Write, true dependency), WAR (Write After Read, anti-dependency), and WAW (Write After Write, output dependency).

13. Which data hazard type is a 'true dependency' and the only one possible in a simple in-order pipeline?

    RAW (Read After Write). WAR and WAW occur only with out-of-order execution or when writes happen in different stage orders.

14. What technique reduces RAW data hazards without stalling by passing ALU results directly between stages?

    Operand forwarding (also called data forwarding or bypassing), which routes a computed result from a later pipeline stage back to an earlier stage that needs it.

15. What is a control (branch) hazard?

    A control hazard occurs because the outcome/target of a branch instruction is not known until later in the pipeline, so the processor may fetch wrong instructions and must stall or flush them.

16. Name three techniques used to handle control hazards.

    Branch prediction (static or dynamic), delayed branching (branch delay slots), and stalling/flushing the pipeline until the branch is resolved.

17. If a branch penalty causes the pipeline to flush, what determines the number of cycles lost?

    The number of stages between instruction fetch and branch resolution; this many cycles' worth of wrongly fetched instructions must be flushed per misprediction.

18. What is the principle of locality of reference that justifies caches?

    Programs tend to access a small portion of memory repeatedly. Temporal locality: recently accessed data is likely to be accessed again soon. Spatial locality: data near a recently accessed location is likely to be accessed soon.

19. Define cache hit ratio and miss ratio.

    Hit ratio $h$ = (number of hits)/(total accesses); miss ratio = $1 - h$. They measure the fraction of memory references found in (or absent from) the cache.

20. What is the formula for average memory access time (AMAT) for a single-level cache?

    $$AMAT = h \cdot t_c + (1-h)(t_c + t_m)$$ or equivalently $$AMAT = t_c + (1-h)\cdot t_m$$ where $t_c$ is cache access time, $t_m$ is main-memory access time, and $h$ is the hit ratio.

21. What are the three cache mapping techniques?

    Direct mapping (each block maps to exactly one cache line), Fully associative mapping (a block can go in any line), and Set-associative mapping (a block maps to one set, but any line within that set).

22. In direct-mapped cache, how is a physical address divided?

    Into three fields: Tag, Line (index) number, and Block/word offset. The line bits select the cache line; the tag is compared to validate the block; the offset selects the word within the block.

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