CSS Computer Science Computer Architecture, Operating Systems & Networks Syllabus

Computer Architecture, Operating Systems & Networks syllabus — full chapter and topic list

Expand any chapter to see its topics and sub-topics. This is the whole examinable outline for Computer Architecture, Operating Systems & Networks in CSS Computer Science, not a summary of it.

1. 1

   Computer Organization & Architecture

   4 topics

   • Performance Metrics & Architectural Levels
   • Machine Instructions & Execution Cycle
   • CISC vs RISC
   • Data Representation & Arithmetic
2. 2

   Processor & Memory Systems

   4 topics

   • Control Unit & Microprogramming
   • Memory Hierarchy
   • Instruction-Level Parallelism
   • Superscalar, Multicore & Multiprocessor Systems
3. 3

   Operating Systems Concepts

   4 topics

   • OS Roles, Structures & Evolution
   • Process Management
   • Memory Management & Virtual Memory
   • File Systems & I/O Management
4. 4

   Computer Communications & Networks

   6 topics

   • Switching & Multiplexing
   • OSI & TCP/IP Models
   • Application Layer Protocols
   • Transport Layer
   • Network Layer
   • Network Security & Special Topics

Computer Architecture, Operating Systems & Networks flashcards for CSS Computer Science

21 of 60 cards from the Computer Architecture, Operating Systems & Networks deck — real questions with worked answers.

1. What is the formula for CPU execution time in terms of instruction count, CPI, and clock cycle time?

   CPU Time = Instruction Count x CPI (cycles per instruction) x Clock Cycle Time = (Instruction Count x CPI) / Clock Rate.

2. State the Iron Law of processor performance and its three factors.

   CPU Time = Instructions/Program x Cycles/Instruction x Seconds/Cycle. The three factors are instruction count, CPI, and clock cycle time. Improving one without worsening others raises performance.

3. Define MIPS as a performance metric and state its main weakness.

   MIPS = (Instruction Count) / (Execution Time x 10^6) = Clock Rate / (CPI x 10^6). Weakness: it cannot compare machines with different instruction sets and can vary across programs, so it is an unreliable absolute metric.

4. State Amdahl's Law and what it implies about speedup.

   Speedup = 1 / [(1 - f) + f/s], where f is the fraction enhanced and s is the speedup of that fraction. It implies overall speedup is limited by the unenhanced portion; if f is small, even infinite s gives little gain.

5. List the levels of abstraction (architectural levels) in a computer system from high to low.

   Application/HLL programs, High-level language, Assembly language, Operating system / Instruction Set Architecture (ISA), Microarchitecture, Logic/digital circuits, and Physical/device level.

6. Distinguish computer architecture (ISA) from computer organization (microarchitecture).

   Architecture (ISA) is the programmer-visible interface: instructions, registers, addressing modes, data types. Organization is the hardware implementation: control signals, buses, cache design, pipeline structure. Different organizations can share one architecture.

7. What are the typical fields of a machine instruction?

   An opcode (operation to perform) and one or more operands/operand specifiers (addresses or register references for source/destination data), sometimes with addressing-mode bits and an immediate value.

8. List the stages of the basic instruction (machine) cycle.

   Fetch the instruction from memory, Decode it, Fetch operands, Execute the operation, and Store/Write-back the result. Then check for interrupts before the next fetch.

9. What is the role of the Program Counter (PC) and the Instruction Register (IR) in the fetch cycle?

   The PC holds the address of the next instruction; its contents are placed on the address bus, the instruction is read into the IR (Instruction Register) for decoding, and the PC is incremented to point to the following instruction.

10. How does the interrupt cycle modify the basic instruction cycle?

    After execution, the processor checks for pending interrupts. If one exists, it saves the current PC (and state), loads the PC with the interrupt handler's address, services the interrupt, then restores state and resumes.

11. Compare CISC and RISC philosophies in terms of instructions and complexity.

    CISC has many complex, variable-length instructions, rich addressing modes, and microcoded control (e.g., x86). RISC has few simple fixed-length instructions, load/store architecture, many registers, hardwired control, and one-cycle execution (e.g., ARM, MIPS).

12. What is a load/store architecture and which design (RISC/CISC) uses it?

    A load/store architecture allows only load and store instructions to access memory; all arithmetic/logic operations work on registers. It is characteristic of RISC designs and simplifies pipelining.

13. Why does RISC typically have a higher instruction count but lower CPI than CISC?

    RISC breaks complex tasks into many simple instructions (higher count) but each executes in roughly one cycle, enabling pipelining (low CPI). CISC has fewer instructions but each can take many cycles (high CPI).

14. How is a signed integer represented in two's complement, and how do you negate a value?

    In two's complement, the most significant bit is the sign; positive numbers are normal binary, negatives are formed by inverting all bits and adding 1. To negate: invert all bits then add 1. Range for n bits: -2^(n-1) to 2^(n-1)-1.

15. Describe the IEEE 754 single-precision floating-point format.

    32 bits: 1 sign bit, 8 exponent bits (bias 127), and 23 fraction (mantissa) bits with an implicit leading 1. Value = (-1)^s x 1.fraction x 2^(exponent-127).

16. What is the exponent bias in IEEE 754, and why is biased representation used?

    Bias is 127 (single) and 1023 (double). The stored exponent = actual exponent + bias. Biasing makes exponents always non-negative, allowing simple unsigned comparison/sorting of floating-point magnitudes.

17. How does a carry differ from an overflow in binary arithmetic?

    A carry-out occurs from the most significant bit position in unsigned arithmetic (indicates unsigned out-of-range). Overflow occurs in signed (two's complement) arithmetic when the sign of the result is incorrect, e.g., adding two positives yields a negative.

18. What is BCD (Binary Coded Decimal) and one advantage of it?

    BCD encodes each decimal digit in its own 4-bit binary code (0000-1001). Advantage: exact representation of decimal fractions and easy conversion to/from human-readable decimal, useful in financial/calculator applications.

19. Contrast the function of the control unit with the datapath.

    The datapath performs data operations (ALU, registers, buses). The control unit generates the timing and control signals that direct the datapath: it decodes instructions and sequences the micro-operations that execute them.

20. Differentiate hardwired control from microprogrammed control.

    Hardwired control uses fixed combinational/sequential logic (gates, state machines) - fast but hard to modify, used in RISC. Microprogrammed control stores control signals as microinstructions in control memory - flexible and easier to design, used in CISC.

21. What is a microinstruction and what does a microprogram represent?

    A microinstruction is a set of control signals (micro-operations) issued in one clock; it may contain a next-address field. A microprogram is the sequence of microinstructions in control memory that implements one machine (macro) instruction.

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