GATE Physics Electronics Syllabus

State the ideal diode (Shockley) equation.

$$I = I_0\left(e^{\,qV/k_BT} - 1\right) = I_0\left(e^{\,V/V_T} - 1\right)$$ where $I_0$ is the reverse saturation current and $V_T = k_BT/q$.

How does the reverse saturation current $I_0$ of a PN diode depend on temperature qualitatively?

$I_0 \propto n_i^{2} \propto T^{3}\exp(-E_g/k_BT)$, so it rises strongly with temperature — roughly doubling about every 10 °C for silicon.

What is the depletion (junction) capacitance of a reverse-biased PN junction and how does it vary with bias?

$$C_j = \frac{\varepsilon_s A}{W} \propto (V_{bi}-V)^{-1/2}$$ for an abrupt junction. Capacitance decreases as reverse bias increases (basis of the varactor diode).

Distinguish avalanche breakdown from Zener breakdown in a reverse-biased diode.

Avalanche: impact ionization in lightly doped, wide junctions; breakdown voltage increases with temperature (positive temp. coefficient). Zener: quantum tunneling in heavily doped, narrow junctions ($\lesssim 5$ V); breakdown voltage decreases with temperature (negative temp. coefficient).

Name the two BJT types and their basic operating principle.

NPN and PNP. A BJT is a current-controlled device: a small base current controls a large collector current via minority-carrier injection across the forward-biased base-emitter junction, collected by the reverse-biased base-collector junction.

For a BJT in active mode, relate the currents and define $\alpha$ and $\beta$.

$$I_E = I_C + I_B,\quad \alpha = \frac{I_C}{I_E},\quad \beta = \frac{I_C}{I_B}$$ with $$\beta = \frac{\alpha}{1-\alpha},\qquad \alpha = \frac{\beta}{\beta+1}$$

List the four BJT operating regions by the bias state of each junction.

Active: BE forward, BC reverse (amplifier). Saturation: both forward (switch ON). Cutoff: both reverse (switch OFF). Reverse-active: BE reverse, BC forward.

What is the transconductance $g_m$ of a BJT in active mode?

$$g_m = \frac{I_C}{V_T} = \frac{q I_C}{k_BT}$$ It gives the small-signal collector current change per unit base-emitter voltage change.

What is the Early effect in a BJT?

Base-width modulation: increasing $V_{CE}$ widens the collector depletion region, narrowing the effective base, which increases $I_C$. Extrapolated $I_C$–$V_{CE}$ lines meet at $-V_A$, the Early voltage. Output resistance $r_o \approx V_A/I_C$.

Name the three BJT amplifier configurations and the key property of each.

Common-emitter: high voltage and current gain, $180^\circ$ phase inversion. Common-base: high voltage gain, current gain $\approx 1$, good high-frequency response. Common-collector (emitter follower): voltage gain $\approx 1$, high current gain, used as buffer (high $Z_{in}$, low $Z_{out}$).

What is the basic operating principle of a JFET?

A JFET is a voltage-controlled, majority-carrier device. The reverse-biased gate-channel junction widens its depletion region with increasing $|V_{GS}|$, narrowing the conducting channel and reducing drain current, until pinch-off.

Write the JFET drain current in the saturation (pinch-off) region.

$$I_D = I_{DSS}\left(1-\frac{V_{GS}}{V_P}\right)^{2}$$ where $I_{DSS}$ is the saturation current at $V_{GS}=0$ and $V_P$ is the pinch-off voltage.

Distinguish enhancement-mode from depletion-mode MOSFETs.

Enhancement-mode: no channel at $V_{GS}=0$; a gate voltage beyond $V_T$ must be applied to create (enhance) the channel. Depletion-mode: channel exists at $V_{GS}=0$; gate voltage can deplete or enhance it.

Write the drain current of an n-channel MOSFET in saturation and the saturation condition.

$$I_D = \frac{1}{2}\mu_n C_{ox}\frac{W}{L}\left(V_{GS}-V_T\right)^{2}$$ valid when $V_{DS} \ge V_{GS}-V_T$ (saturation/active region).

Write the MOSFET drain current in the triode (linear) region.

$$I_D = \mu_n C_{ox}\frac{W}{L}\left[(V_{GS}-V_T)V_{DS} - \frac{V_{DS}^{2}}{2}\right]$$ valid for $V_{DS} < V_{GS}-V_T$.

Compare BJT and FET as amplifying devices on three key points.

BJT: current-controlled, bipolar (both carriers), higher $g_m$ for given current, lower input impedance, has offset/saturation voltage. FET: voltage-controlled, unipolar (majority carriers only), very high input impedance, lower noise, no minority-storage, and no thermal-runaway issue (negative temp. coefficient).

In a feedback amplifier, what is the closed-loop gain and the meaning of negative feedback?

$$A_f = \frac{A}{1+A\beta}$$ Negative feedback ($A\beta>0$ here) reduces gain but improves stability, bandwidth, and linearity; $\beta$ is the feedback factor and $A\beta$ is the loop gain.

List four benefits of negative feedback in amplifiers.

1) Gain stabilization/desensitization (gain less dependent on device parameters). 2) Reduced distortion and noise. 3) Increased bandwidth (gain-bandwidth product constant). 4) Controlled (raised or lowered) input/output impedances depending on topology.

How does negative feedback affect bandwidth, and what quantity stays constant?

It increases bandwidth by the factor $(1+A\beta)$: $f_{H,f} = f_H(1+A\beta)$. The gain-bandwidth product $A\cdot f_H$ remains approximately constant.

State the Barkhausen criterion for sustained oscillations.

For steady oscillation the loop gain must satisfy: magnitude $|A\beta| = 1$ and total phase shift around the loop $= 0^\circ$ (or an integer multiple of $360^\circ$).

Give the oscillation frequency of a Wien-bridge oscillator (equal R and C).

$$f = \frac{1}{2\pi RC}$$ The amplifier must provide a gain of at least 3 to satisfy the Barkhausen criterion.

Give the oscillation frequency of an LC (Hartley/Colpitts) tank and the distinguishing feature of each.

$$f = \frac{1}{2\pi\sqrt{LC}}$$ Colpitts uses a tapped capacitor pair ($C_{eq}$ from $C_1,C_2$ in series); Hartley uses a tapped inductor pair ($L_{eq}=L_1+L_2$).

State the two ideal op-amp 'golden rules' and key ideal parameters.

Rules (with negative feedback): (1) no current flows into the inputs; (2) the two input voltages are equal (virtual short). Ideal parameters: infinite open-loop gain, infinite input impedance, zero output impedance, infinite bandwidth and CMRR.

Give the closed-loop gain of inverting and non-inverting op-amp amplifiers.

Inverting: $$A_v = -\frac{R_f}{R_1}$$ Non-inverting: $$A_v = 1 + \frac{R_f}{R_1}$$

Write the output of an ideal op-amp integrator and differentiator.

Integrator: $$v_o(t) = -\frac{1}{RC}\int v_{in}\,dt$$ Differentiator: $$v_o(t) = -RC\,\frac{dv_{in}}{dt}$$

Define CMRR and slew rate for an op-amp.

CMRR (common-mode rejection ratio): $\text{CMRR} = \left|\dfrac{A_d}{A_{cm}}\right|$, often in dB; ratio of differential to common-mode gain. Slew rate: $SR = \left.\dfrac{dv_o}{dt}\right|_{max}$, the maximum output voltage rate of change (V/µs).

Classify active filters by their frequency response (four basic types).

Low-pass (passes below $f_c$), High-pass (passes above $f_c$), Band-pass (passes a band), Band-stop/notch (rejects a band). 'Active' means they use op-amps plus R and C (no inductors).

For a first-order RC active filter, give the cutoff frequency and roll-off rate.

$$f_c = \frac{1}{2\pi RC}$$ Roll-off is $20$ dB/decade ($6$ dB/octave) per pole; an $n$-th order filter rolls off at $20n$ dB/decade.

Define the quality factor $Q$ of a band-pass filter.

$$Q = \frac{f_0}{\text{BW}} = \frac{f_0}{f_H - f_L}$$ where $f_0$ is the center frequency and BW is the $-3$ dB bandwidth. Higher $Q$ means a narrower, more selective passband.

State De Morgan's theorems of Boolean algebra.

$$\overline{A+B} = \bar{A}\cdot\bar{B}, \qquad \overline{A\cdot B} = \bar{A} + \bar{B}$$ The complement of a sum is the product of complements, and vice versa.

Why are NAND and NOR gates called universal gates?

Because any Boolean function (and hence any logic gate: NOT, AND, OR) can be implemented using only NAND gates, or only NOR gates.

Write the truth-table outputs of a half-adder.

For inputs $A,B$: Sum $= A \oplus B$ and Carry $= A\cdot B$. A full adder adds a carry-in: $S = A\oplus B\oplus C_{in}$, $C_{out} = AB + C_{in}(A\oplus B)$.

What is the key difference between combinational and sequential logic circuits?

Combinational: output depends only on present inputs (no memory), e.g. adders, multiplexers, decoders. Sequential: output depends on present inputs and past state (has memory via flip-flops), and usually requires a clock, e.g. counters, registers.

Give the characteristic (next-state) equations of SR, D, JK, and T flip-flops.

SR: $Q_{n+1} = S + \bar{R}Q_n$ (with $SR=0$). D: $Q_{n+1} = D$. JK: $Q_{n+1} = J\bar{Q}_n + \bar{K}Q_n$. T: $Q_{n+1} = T\oplus Q_n$ (toggles when $T=1$).

What is the forbidden/invalid input condition of an SR latch, and how does the JK flip-flop fix it?

SR latch: $S=R=1$ is forbidden (indeterminate output). The JK flip-flop replaces this with a defined TOGGLE action: when $J=K=1$, $Q_{n+1}=\bar{Q}_n$.

What is the master-slave flip-flop and the problem it solves?

Two latches in series clocked on opposite phases. It eliminates the 'race-around' condition (multiple toggles in one clock pulse) of a level-triggered JK flip-flop by making the output change only once per clock edge.

Describe the operation of a 555 timer in astable mode and its frequency.

In astable mode it free-runs as an oscillator (no stable state), producing a continuous square wave. Frequency: $$f = \frac{1.44}{(R_A + 2R_B)C}$$ with duty cycle $D = \dfrac{R_A+R_B}{R_A+2R_B}$.

Describe the 555 timer in monostable mode and its output pulse width.

It has one stable state and produces a single timed output pulse when triggered. Pulse width: $$T = 1.1\,RC$$

Distinguish asynchronous (ripple) counters from synchronous counters.

Asynchronous/ripple: each flip-flop is clocked by the previous stage's output, so transitions ripple through — simple but slow with cumulative delay. Synchronous: all flip-flops share a common clock, so they change simultaneously — faster, no ripple, but more logic.

How many flip-flops are needed for a modulo-$N$ counter, and what is the maximum count of an $n$-flip-flop binary counter?

Number of flip-flops $= \lceil \log_2 N \rceil$. An $n$-flip-flop binary counter counts $0$ to $2^{n}-1$, i.e. $2^{n}$ states (modulo-$2^{n}$).

List the four basic data-movement modes of a shift register.

SISO (serial-in serial-out), SIPO (serial-in parallel-out), PISO (parallel-in serial-out), and PIPO (parallel-in parallel-out). They store and shift binary data, used for serial/parallel conversion.

Distinguish a ring counter from a Johnson (twisted-ring) counter.

Ring counter: feeds $Q$ of the last flip-flop to the first; an $n$-bit ring counter has $n$ states. Johnson counter: feeds $\bar{Q}$ of the last back to the first; an $n$-bit Johnson counter has $2n$ states.

Write the analog output of a binary-weighted / R-2R N-bit DAC.

$$V_{out} = V_{ref}\sum_{i=0}^{N-1} \frac{b_i}{2^{N-i}} = V_{ref}\,\frac{D}{2^{N}}$$ where $b_i$ are the bits and $D$ is the decimal equivalent of the input code.

Define the resolution (step size) of an N-bit DAC/ADC over a full-scale range $V_{FS}$.

$$\text{Resolution} = \frac{V_{FS}}{2^{N}-1}\approx\frac{V_{FS}}{2^{N}}$$ This is the smallest voltage change (1 LSB) the converter can represent, with $2^{N}$ total levels.

Compare flash, successive-approximation, and dual-slope ADCs on speed and use.

Flash: fastest (one clock), uses $2^{N}-1$ comparators, costly — for high-speed apps. Successive-approximation (SAR): medium speed ($N$ clocks), good speed/cost balance — most common. Dual-slope (integrating): slowest but very accurate and noise-immune — for digital meters.

What is quantization error in an ADC and its maximum value?

The error from mapping a continuous analog value to the nearest discrete level. With rounding, the maximum quantization error is $\pm\frac{1}{2}$ LSB, i.e. $\pm\dfrac{V_{FS}}{2^{N+1}}$.