GATE E&C Engineering Digital Circuits Syllabus

In static CMOS, how is a series connection of NMOS in the PDN reflected in the PUN?

Series NMOS in the PDN corresponds to parallel PMOS in the PUN (the two networks are duals).

Why does an ideal static CMOS gate draw essentially no static (DC) power?

Because in any steady logic state either the PUN or the PDN is off, so there is no direct path from $V_{DD}$ to ground; power is dissipated mainly during switching.

Write the sum and carry equations of a half adder.

$S = A\oplus B$ and $C_{out}=A\cdot B$.

Write the sum and carry-out equations of a full adder.

$S = A\oplus B\oplus C_{in}$ and $C_{out}=AB + C_{in}(A\oplus B)$.

What is the main speed limitation of a ripple-carry adder?

The carry must propagate through all stages serially, so worst-case delay grows linearly as $O(n)$ with the number of bits.

In a carry-look-ahead adder, define the generate and propagate signals.

Generate $G_i = A_i B_i$ and propagate $P_i = A_i\oplus B_i$; carry $C_{i+1}=G_i + P_i C_i$, allowing carries to be computed in parallel.

How is binary subtraction $A-B$ performed using 2's complement addition?

Compute $A + (\text{2's complement of } B) = A + \bar B + 1$ and discard the final carry-out.

What distinguishes Gray code from standard binary code?

In Gray code, successive numbers differ in exactly one bit, which minimizes errors in transitions (e.g. shaft encoders).

Give the rule to convert binary $B$ to Gray code $G$.

$G_{n-1}=B_{n-1}$ and $G_i = B_{i+1}\oplus B_i$ for the remaining bits (MSB copied, then XOR adjacent bits).

Give the rule to convert Gray code $G$ back to binary $B$.

$B_{n-1}=G_{n-1}$ and $B_i = B_{i+1}\oplus G_i$ (running XOR from MSB downward).

What is a $2^{n}$-to-$1$ multiplexer and how many select lines does it need?

A circuit that routes one of $2^{n}$ data inputs to the output based on $n$ select lines; output $=\sum (\text{minterm of selects})\cdot D_i$.

How can a multiplexer be used to implement an arbitrary Boolean function?

A $2^{n}$-to-1 MUX with the $n$ variables on the select lines and the truth-table output values (0,1, a variable, or its complement) on the data inputs realizes any function of $n$ variables.

What does an $n$-to-$2^{n}$ decoder do?

It activates exactly one of $2^{n}$ output lines corresponding to the $n$-bit input code; each output is a distinct minterm of the inputs.

How can a decoder with an OR gate implement Boolean functions?

A full decoder generates all minterms; ORing the required minterm outputs gives any SOP function (decoder outputs act as minterm generators).

What is the key functional difference between a latch and a flip-flop?

A latch is level-sensitive (transparent while the enable/clock level is active); a flip-flop is edge-triggered (state changes only on a clock edge).

Describe the behavior of an SR latch including its forbidden input.

$S=1,R=0\Rightarrow Q=1$; $S=0,R=1\Rightarrow Q=0$; $S=R=0\Rightarrow$ hold; $S=R=1$ is forbidden (invalid/indeterminate output).

Give the characteristic equation of a D flip-flop and a JK flip-flop.

D flip-flop: $Q_{next}=D$. JK flip-flop: $Q_{next}=J\bar Q + \bar K Q$.

What does a T (toggle) flip-flop do, and what is its characteristic equation?

When $T=1$ it toggles, when $T=0$ it holds: $Q_{next}=T\oplus Q$.

What is the modulus of a counter, and how many flip-flops are needed for a mod-$N$ counter?

The modulus is the number of distinct states before repeating. A mod-$N$ counter needs at least $\lceil \log_2 N\rceil$ flip-flops.

Compare synchronous and asynchronous (ripple) counters.

In synchronous counters all flip-flops share one clock, so they switch together (faster, no cumulative delay). In ripple counters the clock of each stage comes from the previous output, causing cumulative propagation delay.

What is the maximum clock frequency limit of a ripple counter with $n$ flip-flops each of delay $t_{pd}$?

Worst case the carry ripples through all stages, so $f_{max}\approx \frac{1}{n\cdot t_{pd}}$ (delays add).

What is a ring counter and how many states does it have for $n$ flip-flops?

A circular shift register where the output feeds back to the input; a single 1 (or 0) circulates, giving $n$ unique states.

What is a Johnson (twisted-ring) counter and its number of states for $n$ flip-flops?

A ring counter where the complemented output feeds back to the input, producing $2n$ unique states.

List the four basic data-movement modes of a shift register.

SISO (serial-in serial-out), SIPO (serial-in parallel-out), PISO (parallel-in serial-out), and PIPO (parallel-in parallel-out).

What is the difference between a Mealy and a Moore finite state machine?

In a Moore FSM the output depends only on the current state; in a Mealy FSM the output depends on both the current state and the present inputs. Mealy often needs fewer states but its outputs can change asynchronously with inputs.

What three elements define a finite state machine?

A set of states, a next-state (transition) function of current state and inputs, and an output function. It is realized with state registers plus combinational next-state and output logic.

Define propagation delay ($t_{pd}$) of a logic gate.

The time between an input transition crossing 50% and the resulting output transition crossing 50%; often averaged as $t_{pd}=\frac{t_{pHL}+t_{pLH}}{2}$.

Define setup time and hold time of a flip-flop.

Setup time $t_{su}$ is the minimum interval the data must be stable before the clock edge; hold time $t_{h}$ is the minimum interval the data must remain stable after the clock edge. Violations cause metastability.

What is the critical path of a synchronous circuit and how does it set the maximum clock frequency?

The critical path is the longest combinational delay between registers. The clock period must satisfy $T_{clk}\geq t_{cq}+t_{comb,max}+t_{su}$, so $f_{max}=\frac{1}{t_{cq}+t_{comb,max}+t_{su}}$.

What is the hold-time constraint in a synchronous circuit?

$t_{cq}+t_{comb,min}\geq t_{h}$; the shortest combinational path plus clock-to-Q delay must exceed the hold time, otherwise new data corrupts the capture (independent of clock period).

What is the function of a sample-and-hold circuit in a data-acquisition system?

It samples (tracks) the analog input at a sampling instant and holds that value constant on a capacitor during the conversion time, so the ADC sees a stable input despite a changing signal.

For an $n$-bit ADC with full-scale voltage $V_{FS}$, what is the resolution (LSB size)?

$\text{LSB} = \frac{V_{FS}}{2^{n}}$, and the maximum quantization error is $\pm\frac{1}{2}\text{LSB}$.